Electrostatic discharge (ESD) can damage integrated circuits (ICs). ESD is caused when a source of electrostatic potential (e.g., a human body with a static buildup of charge carriers) comes into contact with a circuit input. The electrostatic voltage may damage sensitive ICs if the electrostatic voltage discharges through circuit elements. In order to prevent ESD damage to functional circuits on the IC, ESD protective circuits may be incorporated on the input/output (I/O) pads of the IC. The role of an ESD protection circuit is to ensure, that in case of an ESD event, the electrostatic potential is shunted (or diverted) to ground—i.e., the electrostatic potential can be discharged through the ESD protective circuits, protecting the IC's functional circuits.
FIG. 1 illustrates a conventional ESD protection scheme for an IC 100 including an I/O pad 102 and an internal circuit 104. The conventional ESD protection scheme includes ESD protection circuits 106, 108, and an ESD clamp 110. ESD protection circuits 106, 108 are typically formed by diodes (represented by D1 and D2 in FIG. 1). ESD protection circuit 106 couples I/O pad 102 to a high-side supply VDD 112, and ESD protection circuit 108 couples I/O pad 102 to a low-side supply VSS 114. ESD clamp 110 couples VDD 112 to VSS 114, and provides a discharge path between VDD 112 and VSS 114 during an ESD event.
There are four types of ESD events that can occur at I/O pad 102 with respect to VDD 112 and VSS 114. The four types of ESD events are:
(1) I/O pad 102 to VDD 112, positive discharge pulse: An I/O pad 102 to VDD 112 positive discharge pulse occurs when a positive ESD exerts stress on I/O pad 102 with VDD 112 relatively grounded. VSS 114 floats during an I/O pad 102 to VDD 112 positive discharge pulse. As discussed above, the role of an ESD protection circuit is to shunt ESD away from an IC's functional circuits. The I/O pad 102 to VDD 112 positive ESD is shunted away from internal circuit 104 as follows: ESD protection circuit 106 shunts ESD current (associated with the positive discharge pulse) from I/O pad 102 to VDD 112.
(2) I/O pad 102 to VDD 112, negative discharge pulse: An I/O pad 102 to VDD 112 negative discharge pulse occurs when a negative ESD exerts stress on I/O pad 102 with VDD 112 relatively grounded. VSS 114 floats during an I/O pad 102 to VDD 112 negative discharge pulse. The I/O pad 102 to VDD 112 negative ESD is shunted away from internal circuit 104 as follows: ESD clamp 110 shunts ESD current (associated with the negative discharge pulse) from VDD 112 to VSS 114. ESD protection circuit 108 shunts the ESD current from VSS 114 to I/O pad 102.
(3) I/O pad 102 to VSS 114, positive discharge pulse: An I/O pad 102 to VSS 114 positive discharge pulse occurs when a positive ESD exerts stress on I/O pad 102 with VSS 114 relatively grounded. VDD 112 floats during an I/O pad 102 to VSS 114 positive discharge pulse. The I/O pad 102 to VSS 114 positive ESD is shunted away from internal circuit 104 as follows: ESD protection circuit 106 shunts ESD current (associated with the positive discharge pulse) from I/O pad 102 to VDD 112. ESD clamp 110 shunts ESD current from VDD 112 to VSS 114.
(4) I/O pad 102 to VSS 114, negative discharge pulse: An I/O pad 102 to VSS 114 negative pulse occurs when a negative ESD exerts stress on I/O pad 102 with VSS 114 relatively grounded. VDD 112 floats during an I/O pad 102 to VSS 114 negative discharge pulse. The I/O pad 102 to VSS 114 negative ESD is shunted away from internal circuit 104 as follows: ESD protection circuit 108 shunts ESD current (associated with the negative discharge pulse) from VSS 114 to I/O pad 102.
The conventional ESD protection scheme described above can generally shunt potentially damaging electrostatic potential away from sensitive circuitry (e.g., internal circuit 104). One limitation of the conventional ESD protection scheme is a large parasitic capacitance that is typically associated with each of ESD protection circuits 106, 108. Such a large parasitic capacitance can couple noise appearing on VDD 112—i.e., high-side supply noise—through ESD protection circuit 106 to internal circuit 104, and adversely affect the performance and reliability of internal circuit 104.